Non-volatile semiconductor data storage devices, such as read only memories (“ROMs”), are designed to store data in a ROM array of memory “cells”. Each memory cell, consisting of a single transistor per bit of storage, is hardware preprogrammed during the integrated circuit (“IC”) fabrication process and is capable of maintaining the stored data indefinitely, even in the absence of power. ROM memories may be included in any type of IC, such as an IC that substantially contains only ROM memory, as a dedicated ROM IC, or included as an “embedded” memory as part of an IC containing additional, other substantial circuits, such as embedded ROM memory with a processor, digital signal processor, controller, wireless telecommunication or other communication IC. In general, ROM memory is used to hold and make available data or code that will not be altered after IC manufacture. Data or code is programmed into ROM memory during fabrication.
A ROM array of memory cells is defined by a number of transistors generally arranged in a grid pattern having a plurality (or series) of rows and columns. Each individual transistor of each memory cell of the ROM array is placed between a column of the series of columns and a voltage bus. The column is supplied with power at a first predetermined voltage level, referred to as the “pre-charged voltage level”, “VPC”, and the voltage bus is supplied with power at a second, different predetermined voltage level. For the sake of clarity, this voltage bus will be referred to as the “source voltage bus”, which has the second predetermined voltage level; the source voltage bus with its second predetermined voltage level will be referred to as “Vsvb”. Common values for these first and second predetermined voltage levels typically depend upon the selected ROM implementation. For example, when the transistors of the array are n-channel, the column is typically pre-charged to a first predetermined voltage level (VPC) substantially equal to a power supply voltage (“Vdd”) or another selected pre-charged voltage level, while the second predetermined voltage level (Vsvb) is ground or zero volts. Vsvb, however, could have other non-zero values. For example, when the transistors of the array are p-channel, the column is typically pre-charged to the first predetermined voltage level (VPC) substantially equal to a ground potential, zero volts or another selected pre-charged voltage level, while the second predetermined voltage level (Vsvb) is substantially equal to a power supply voltage (“Vdd”) or another selected pre-charged voltage level.
A gate of each transistor of a ROM array is connected to a particular row of the series of rows. In the prior art, a source of each transistor is always connected to the source voltage bus, and a drain of each transistor is or is not connected to a particular column of the series of columns, depending upon how the cell is to be programmed. The ROM array is programmed during fabrication by the presence or absence of such a drain-to-column connection (a drain-to-column “contact window”). As indicated above, each column of the series of columns is typically pre-charged to a first predetermined voltage potential referred to as the “pre-charged voltage level”, VPC. This voltage level is different than that of the source voltage bus, Vsvb. Typically, VPC may be a voltage higher than ground or higher than 0 volts (a positive or high voltage). The column residing at the pre-charge voltage represents a first logical state such referred to as a “1” data state or a first data state, and is subject to operation of its associated transistor(s).
In the prior art, the memory cells of a ROM array are preprogrammed via the presence or absence of a contact window between their transistor drains and their corresponding columns, while all sources are coupled to the source voltage bus. All columns are pre-charged to the pre-charged voltage level VPC. When a “1” data state is desired for a particular bit stored on a particular transistor, no contact is made between that transistor drain and its corresponding column (i.e., absence of the contact window). As a consequence, the column continues to maintain its pre-charged voltage when a row connected to that transistor gate (i.e., a corresponding row) is activated, given the absence of a drain contact to the column. In contrast, when a second logical state referred to as a “0” data state or a second data state is desired for the particular bit stored on a particular transistor, given that its drain is coupled to its corresponding column via the contact window, when the row connected to that transistor gate (i.e., a corresponding row) is activated and the transistor conducts, that column voltage is moved or pulled to the potential of the source voltage bus, Vsvb. That column, therefore, does not maintain its pre-charged voltage level associated with the logical high or first data state, but now represents a logical low or second data state.
To obtain information from a ROM, by a “Read” operation, a row is activated. All transistors along that row are activated via their respective gates. Along the activated row, all of the transistors that have been programmed to a “0” data state move their respective columns towards Vsvb potential. All transistors that have been programmed to a “1” data state will not change the voltage of their associated columns. Their column voltages remain at VPC. The different voltage levels, VPC and Vsvb, are sensed from selected columns, such as for a byte or word of information, using sense amplifiers. Even though all of the columns along a row are activated, only some of the columns are “selected” for output; that is, their data represented by their corresponding voltage levels are forwarded to the output of the memory. The selected columns are typically arranged in a periodic order throughout the population of columns (e.g., reading from every eighth column). A particular data word is selected through appropriately addressing a selected row and selected columns.
With increasing cell density and decreasing feature size, adjacent columns may interact, potentially resulting in read errors. For example, as feature sizes may be reduced using a 0.16 micron or smaller fabrication technology, errors may result from an interaction between a selected column and its adjacent or nearby columns due to capacitive coupling. Such undesirable capacitive coupling between a selected column and its neighboring columns may cause increased memory “read faults”.
In order to simplify the following description, VPC will be assumed to be a positive or high voltage level and Vsvb will be assumed to be ground voltage potential. Capacitive coupling read faults can occur when a column, associated with reading a “1” data state programmed cell, is activated or “selected”, and its neighboring column, associated with reading a “0” data state programmed cell, is pulled to ground. Furthermore, more than one neighboring column may interact in this way with the selected column. Capacitive coupling between the selected column and one or more neighboring columns may cause the voltage level of the selected column to be pulled below its desired, pre-charged positive or high voltage level and appear as a low voltage (“0” data state) rather than a positive or high voltage (“1” data state) to its associated sense amplifier, resulting in a read error for that stored bit. Capacitive coupling between columns can cause the same type of read failures regardless of the operational voltage levels for VPC and Vsvb.
In the prior art, read errors that could occur due to capacitive coupling have been avoided by maintaining relatively large physical separation or spacing between array features such as the array columns, resulting in lower cell densities on an integrated circuit. Such increased distance (or physical separation) between features is not a viable alternative for eliminating read errors when increased density, i.e., less physical separation between array features, is required or desired for a ROM architecture.
As a consequence, a need remains to provide a ROM architecture having a reduced feature size and higher cell density, while simultaneously alleviating any read errors which may arise due to capacitive coupling or other interference between or among array features, such as capacitive coupling between neighboring or adjacent array columns.